In their simplest implementation, a magnetic random memory (MRAM) cell comprises a magnetic tunnel junction formed from a thin insulating layer sandwiched between a first magnetic layer, or reference layer, characterized by a fixed magnetization and a second magnetic layer, or storage layer, characterized by a magnetization which direction can be changed upon writing of the MRAM cell. When the respective magnetizations of the reference and storage layers are oriented antiparallel, the magnetic tunnel junction resistance is high (Rmax). On the other hand, when the respective magnetizations of the reference and storage layers are oriented parallel, the magnetic tunnel junction resistance becomes low (Rmin). The MRAM cell is read by comparing its junction resistance to the junction resistance of a reference cell, or several reference cells, Rref, having a junction resistance of Rref=(Rmin+Rmax)/2.
It has also been proposed to use magnetic tunnel junctions in logic elements wherein the magnetic junction is used to store the results of the operation or to define the functionality of the logic element (see for instance “Fabrication of a Nonvolatile Full Adder Based on Logic-in-Memory Architecture Using Magnetic Tunnel Junctions” by Matsunaga et. al., Appl. Phys. Exp. 1 (2008) 091301). The description below is described for MRAM element but it will be obvious for the man skilled in the art to translate it to logic type of applications.
The MRAM cell can be written, by switching the magnetization direction of the storage layer, using different write operation schemes. In a first write operation scheme, two magnetic fields are applied coincidently in a cross-point architecture as described in U.S. Pat. No. 5,640,343, No. 6,430,085 and No. 6,956,763. This write operation scheme can be implemented in different manners that are known as magnetic field switching, Stoner-Wohlfarth Switching, Toggle Switching, Precessional switching, etc.
Alternatively, the MRAM cell can be written by a coincident magnetic field and a thermal pulse as described in U.S. Pat. No. 6,950,335 and No. 6,535,416. This approach is referred to as thermally assisted switching (TAS).
The MRAM cell can also be written using a spin polarized current flowing through the magnetic tunnel junction, as described initially in U.S. Pat. No. 5,695,864 and No. 6,172,902. As the spin polarized current acts as a local (magnetic) torque, this approach is known as spin transfer torque (STT).
Another possible write operation scheme includes a coincident pulse of spin polarized current flowing through the magnetic tunnel junction and a thermal heating current pulse as described in U.S. Pat. No. 6,950,335. This approach is referred to as combined Spin transfer plus Thermally Assisted Switching (STT+TAS).
The write operation scheme based on STT is viewed as the most promising route for high density MRAM device using MRAM cells because the spin polarized write current scales directly with the MRAM cell size, which is not the case in the other write operation scheme implementations. In the STT-based write operation, the switching of the storage layer magnetization depends on the spin polarized current density which scales with the inverse of the area of the MRAM cell. Moreover, switching of the storage layer magnetization with the spin polarized current can be fast and the MRAM cell size can be minimized since no magnetic field line is required.
Most practical implementations of the STT-based write operation so far involve a so-called “longitudinal” configuration, whereupon the spins of the spin polarized current are injected antiparallel (in the same plane or in-plane) as the storage layer magnetization to be switched. This can be done using storage layer materials having in-plane magnetization, i.e., having magnetization in the plane of the layers e.g. wafers, or perpendicular magnetization, e.g. having magnetization out of the plane of the magnetic wafers.
MRAM cells with a STT-based write operation, however, suffers from several drawbacks. For example, the spin polarized write current density required to switch the storage layer magnetization is large (currently ˜4 MA/cm2 for a 10 ns pulse width) and increases dramatically for shorter pulse width. This leads to large and unpractical MRAM cell sizes due to underlying selection transistors sourcing such current densities. It also leads to high power dissipation and to a potential wear and correlated lack of reliability of the magnetic tunnel junction, in particular of the insulating layer.
Moreover, insuring the stability of the data written in the MRAM cell by switching the magnetization of the storage layer requires achieving simultaneously good stability in the storage layer magnetization direction and a small write current in order to avoid the drawbacks above. This is becoming a major issue at feature sizes smaller than 45 nm.
Finally, the write operation speed is limited by the stochastic nature of switching. Indeed, if the intrinsic STT switching speed is fast (in the order of ns), the switching of the magnetization is triggered by thermal activation which is stochastic in nature. As a result, the practical switching time using the STT-based write operation is limited to about 10 ns or longer.
The stability of written data can be improved using perpendicularly magnetized magnetic layers, as recently demonstrated by Nakayama et al., Journ. Appl. Phys. 103, 07A710 (2008). Alternatively, a good tradeoff between stability of written data and write current can be obtained by using a combination of TAS and STT, as proposed in U.S. Pat. No. 6,950,335. None of these solutions, however, allows for a reduction in the write current density.
In order to decrease the write current density, several approaches have been proposed: more particularly, U.S. Pat. No. 6,603,677 proposes using a synthetic antiferromagnetic (SAF) multilayer as storage layer. The corresponding decrease of the current density is small (about 3 MA/cm2 at 10 ns pulse width) but the true benefit is a more coherent internal magnetization in the magnetic cell, leading to a narrower current distribution within the magnetic cell array.
In their publication, Hayakawa et al., Jap. Journ. Appl. Phys. 44 (2005) L1247, describes a method for decreasing the saturation magnetization of the storage layer. Here, the storage layer is assumed to be magnetized in-plane, and the write current scales directly with saturation magnetization. However, this approach has a severe drawback due to a sharp decrease of stability when the saturation magnetization is decreased caused by a correlative decrease of shape anisotropy. It is therefore not practical beyond a certain limit.
U.S. Patent Application Publication US2006/0141640 discloses using a dual magnetic tunnel junction structure, e.g. two symmetrical spin polarizing layer. This latter approach allows for using writing current in the order of 1 MA/cm2 for a 10 ns pulse width but results in an increased complexity in the magnetic tunnel junction manufacturing process.
In an alternative approach, U.S. Pat. No. 6,532,164 discloses a MRAM cell configuration where the magnetic tunnel junction is formed from an insulating layer disposed between a first magnetic layer having a first magnetization direction, and a second magnetic layer having a second magnetization direction that is adjustable relative to the first magnetization direction. The magnetic tunnel junction also comprises a polarizing layer having a magnetization oriented perpendicular to the magnetization of the first and second magnetic layers. When a write current flows through the magnetic tunnel junction, the polarizing layer orients the spins of the write current perpendicularly to the magnetization of the first and second magnetic layers, and the write current switches the magnetization second magnetic layer through a precession of said magnetization in the plane of the magnetic layer. This configuration enables the use of a low write current density and permits an increased writing speed. However, in such a configuration, the second layer magnetization rotation frequency is in the range of 1 to 20 GHz (see Applied Physics Letters, 86 (2005), 022505) which is too high for any practical application such as in memory devices. Indeed, such high rotation frequencies would require a write current pulse in the sub-nanosecond range, which is too short in large arrays of MRAM cells with parasitic RC time constants.